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EL4544
Data Sheet August 1, 2005 FN7362.1
Triple 16x5 Differential Crosspoint Switch Capable of Operation in Single-Ended or Differential Input Modes
The EL4544 is a high bandwidth 16-channel differential RGB to 5-channel RGB single-ended RGB-HV video crosspoint switch with embedded sync extraction. Four 16-channel input muxes, each capable of receiving a complete RGB video signal, and five output muxes, each capable of "seeing" any one of the four RGB inputs. Additionally, the fifth input mux has an overlay "screen on screen" function that can be displayed in conjunction with any of the stacked RGB inputs. The EL4544 has a fast disable feature to reduce power consumption. The device also provides a presence of signal indicator by looking for syncs on a designated channel.
Features
* Serial programming of switch array * Parallel or serial modes * High Z output disable * Drives 150 loads * 60MHz 0.1dB gain flatness * -3dB bandwidth of 300MHz * Crosstalk rejection: 75dB @ 100MHz * Channels settle to 5% within 10ns after overlay switching * 356-pin BGA packaging * Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER EL4544IGZ (See Note) PACKAGE 356-Pin (27x27mm) BGA (Pb-Free) TAPE & REEL PKG. DWG. # -
Applications
* Video switching
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL4544 Pinout
EL4544 (356-PIN BGA) TOP VIEW
20
Vp Vm Vm BpF BnF BpE BpD BpC BpB BpA BnE BnD BnC BnB BnA Vm Vm Vm Vm Vm Vm Vm Vm Bp9 Bn9 Vm Vm Bp8 Bn8 Vp Vm Bp7 Bn7 Vm Vm Bp6 Bn6 Vm Vm Bp5 Bn5 Vm Vm Bp4 Bn4 Vm Vm Bp3 Bn3 Vm Vm Bp2 Bn2 Vm Vm Bp1 Bn1 Bp0 Bn0 Vm Vm Vp Vm
19
Vm
18
RpF RnF TMon1 Vm RnE Vm Vm Vm Vm Vm Vm Vp Vm Vm Vm Vm RAZ Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm GAZ Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm TMon2 GnF GpF Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm Vm NC Vm Vm Vm Vm Vm Vm Vp Vm Vm Vm Vm NC GnE GpE GnD GpD GnC GpC GnB GpB GnA GpA Gn9 Gn8 Gn7 Gn6 Gn5 Gn4 Gn3 Gp9 Gp8 Gp7 Gp6 Gp5 Gp4 Gp3 Gp2 Gp1 Gp0 VmA RefA
17
RpE
16
RpD RnD
15
RpC RnC
14
RpB RnB
13
RpA RnA
12
Rp9 Rn9 Rn8 Rn7 Rn6 Rn5 Rn4 Rn3
11
Rp8
10
Rp7
9
Rp6
8
Rp5
7
Rp4
6
Rp3
5
Rp2 Rn2 Trans RefOL Rn1 Rn0 Hs Gs Cal Vp Vs Bs ROL Ovl GOL BOL BAZ Vm Hd Gd Vm Vm Vd Bd Vm Vm Vm Vm Vm Vm Hc Gc Vm Vm Vc Bc Vm Vm Vm Vm Vm Vm Hb Gb Vm Vm Vb Bb sDo sDi Vdp Chip Gn2 sEn Reset Gn1 sClk Vp Ha Ga Gn0 Va Ba
4
Rp1
3
Rp0
2
VpS VmS VpD RefS Rd VmD VpC RefD Rc VmC VpB RefC Rb VmB VpA RefB Ra
1
Rs
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
= EMPTY LOCATION (UNPOPULATED) = BALLGRID
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FN7362.1 August 1, 2005
EL4544
Absolute Maximum Ratings (TA = 25C)
VSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VS VSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Recommended Operating Temperature . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY CHARACTERISTICS VSA VSD ISD ISA
VSA = 5V, VSD = 3.3V, Gain = 2, RL = 150, CL = 2.7pF, TA = 25C. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Recommended Analog Supply Voltage Recommended Digital Supply Voltage Digital Supply Current Analog Supply Current Enabled - no load, all amplifiers enabled Disabled
4.75 2.4
5.0 3.3 3 685 33 40
5.25 3.6 10 790 50
V V mA mA mA dB
PSRR
Power Supply Rejection Ratio
4.75V to 5.25V
CHARACTERISTICS OF DIFFERENTIAL INPUTS CMRR AV VN VOS Input Common Mode Rejection Ratio 0V to 1.5V 45 1.85 66 2.0 40 -80 -10 0 5 80 12 VSA 2 1100 1.49 1320 1.53 1550 1.57 2.15 nV/Hz mV mV V pF V dB
Gain Accuracy for A, B, C, D, S Channels Range of Deviation from gain of 2 (excluding overlay) Input Referred Voltage Noise Input Referred Offset Voltage AV = +2 Includes muxes and output amps; A, B, C, D channels S channel in auto-calibration mode
VIN CIN RIN VINSET
Maximum Recommended Input Range Input Capacitance Input Resistance, Single-ended Input Biasing Voltage
OVERLAY INPUT CHARACTERISTICS VOS Input Referred Offset Voltage S channel overlay inputs at AV = 2 -10 5 12 mV
OVERLAY SWITCHING CHARACTERISTICS PAPERTURE AV Pixel Mux Aperture of Uncertainty Gain Accuracy for S Channel 5% setting for max signal charge S channel overlay input 10 ns
OUTPUT CHARACTERISTICS Output Impedance VOUT IOUT Maximum Recommended Output Range Output Current Short-circuit (5) Enabled Disabled 0 60 100 10 3.3 m M V mA
AC PERFORMANCE SR Slew Rate 2VP-P symmetrical, RL = 150, AV = 2, guaranteed by design 800 V/s
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FN7362.1 August 1, 2005
EL4544
Electrical Specifications
PARAMETER BW -3dB Bandwidth 0.1dB Bandwidth Settling Time Crosstalk 1% Settling Time Hostile Crosstalk Between any 2 Channels Worst Case Hostile Crosstalk One Channel Affected by all Other Channels Running the Same Signal VSA = 5V, VSD = 3.3V, Gain = 2, RL = 150, CL = 2.7pF, TA = 25C. (Continued) CONDITION -3dB, 200mVP-P, load of 150 0.1dB, 200mVP-P, load of 150 2VO step, load of 150 100MHz 100MHz MIN TYP 300 60 10 -70 -50 MAX UNIT MHz MHz ns dB dB
DESCRIPTION
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FN7362.1 August 1, 2005
EL4544 I/O Block Diagram of Video Signals
R0 16x2:1 MUX Ai INPUT GAIN SELECTION 2 2 R15 G15 R0 B15 16x2:1 MUX Bi 2 2 R15 G15 R0 B15 16x2:1 MUX Ci 2 2 R15 G15 R0 B15 16x2:1 MUX Di 2 2 R15 G15 B15 SYNC 2 R G B H V SYNC 2 R G B H V SYNC 2 R G B H V SYNC 2 R G B H V 4x5 XPOINT MUX Ai Ax OUTPUT GAIN SELECTION R G B H V 2 2 2 L L OutA = (Ra, Ga, Ba + Ha, Va)
Bi
Bx
R G B H V
2 2 2 L L OutB = (Rb, Gb, Bb + Hb, Vb)
Ci
Cx
R G B H V
2 2 2 L L OutC = (Rc, Gc, Bc + Hc, Vc)
Di
Dx
R G B H V
2 2 2 L L
TRANSPARENT OVERLAY OutD = (Rd, Gd, Bd + Hd, Vd) Ro Go Bo Rs Gs OutS = (Rs, Gs, Bs, Hs, Vs) Bs L L OutSO = (Rso, Gso, Bs, Hs, Vs) Hs Vs 2 2 2 Rso Gso Bso CALIBRATE/HOLD
2:1 PIXEL MUX
Sx Rs
NOTES: 1. Each output group is a 5 element vector (R, G, B + H, V) 2. Each input group is a 3 element vector (R, G, B) 3. All outputs drive back terminated 75 cable
Gs Bs Hs Vs
SDI (SERIAL DATA INPUT) SCLK (SERIAL CLOCK) SEN (SERIAL CLOCK ENABLE/LATCH) CONTROL REGISTERS
SDO (SERIAL DATA OUTPUT)
RESET (CLEARS ALL REGISTERS) WHEN HI, DATA IS CLOCKED IN, WHEN LO, DATA IS LATCHED TO ENABLE SELECTION
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FN7362.1 August 1, 2005
EL4544 I/O Block Diagram of Video Signals with Power Supplies and References
R0 16x2:1 MUX Ai 2 2 R15 G15 R0 B15 16x2:1 MUX Bi 2 2 R15 G15 R0 B15 16x2:1 MUX Ci 2 2 R15 G15 R0 B15 16x2:1 MUX Di 2 2 R15 G15 B15 SYNC 2 R G B H V SYNC 2 R G B H V SYNC 2 R G B H V Bi Bx R G B H V 2 2 2 L L RefB VmB VpC 2 2 2 L L RefC VmC VpD 2 TRANSPARENT 2 2 L Go L RefD VmD Rs Gs Bs Hs Vs OutSO = (Rso, Gso, Bs, Hs, Vs) SDI (SERIAL DATA INPUT) SCLK (SERIAL CLOCK) SEN (SERIAL CLOCK ENABLE/LATCH) CONTROL REGISTERS RESET (CLEARS ALL REGISTERS) WHEN HI, DATA IS CLOCKED IN, WHEN LO, DATA IS LATCHED TO ENABLE SELECTION SDO (SERIAL DATA OUTPUT) OutS = (Rs, Gs, Bs, Hs, Vs) Bo Rs Gs Bs 2:1 PIXEL MUX L L 2 2 2 Rso Gso Bso RefS VmS Hs Vs OVERLAY OutD = (Rd, Gd, Bd + Hd, Vd) Ro CALIBRATE/HOLD OutC = (Rc, Gc, Bc + Hc, Vc) OutB = (Rb, Gb, Bb + Hb, Vb) SYNC 2 R G B H V 4x5 XPOINT MUX Ai Ax R G B H V 2 2 2 L L RefB VmA VpB OutA = (Ra, Ga, Ba + Ha, Va) VpA
Ci
Cx
R G B H V
Di
Dx
R G B H V
VpS
Sx
NOTES: 1. Each output group is a 5 element vector (R, G, B + H, V) 2. Each input group is a 3 element vector (R, G, B) 3. All outputs drive back terminated 75 cable
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FN7362.1 August 1, 2005
EL4544 Serial Bus Interface Architecture
LOAD 4 BIT SELECTOR 0 S0 L O A D 1-SHOT PULSE GENERATOR
SEN
LF3 LF2 LF1 LF0 C L R
LF3 LF2 LF1 LF0
d3 m Sm L O A D
d2
d1
d0
Lm3 Lm2 Lm1 Lm0 C L R
LM3 LM2 LM1 LM0
d3 F SF L O A D
d2
d1
d0
L03 L02 L01 L00 C L R
L03 L02 L01 L00
b3 b2 b1 b0
d3
d2
d1
d0
RESET
ADDRESS
DATA
SDO
Q
D RESET
A3
A2
A1
A0
D3
D2
D1
D0
SDI SCLK SEN
CLEAR
8 BIT SHIFT REGISTER
NOTE: The selector has 16 outputs, connected to 16 AND gates, connected to 16 4-bit latches. Rising edge of SEN triggers the load one-shot.
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FN7362.1 August 1, 2005
EL4544 Serial Bus Interface Timing Diagram
WRITE TO REGISTER OF EL4544 (ADDRESS = XXXX) SEN t(SEN) IDLE
t(SCLK)HI SCLK
t(SCLK)LO
(1/F)*SCLK 8 td(SEN)
SDI
MSB A3 A2 A1
LSB A0
MSB D3 D2 t(SDI) SETUP D1
LSB D0 t(SDI) HOLD
td(SCLK) START CURRENT (m) REGISTER ADDRESS (4 BITS) MSB D0 A3 A2 A1 LSB A0 MSB D3
CURRENT (m) INPUT DATA (4 BITS) LSB D2 D1 D0
PREVIOUS... (m-2) PREVIOUS (m-1) ADDRESS (4 BITS) ADDRESS
PREVIOUS (m-1) DATA (4 BITS)
NOTE: Readback of the serial bus register can be done as follows: After SEN is taken low, latching data, and before writing the next word, the data in the register can be read back by clocking out 8 bits before writing in the next word.
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FN7362.1 August 1, 2005
EL4544 Serial Bus Interface Control Table
HEX ADDRESS CODE 0 1 2 3 4 5 6 7 8 9 A B C D E ADDRESS FUNCTION Ai Input Mux: Select Input of Input Mux Ai Bi Input Mux: Select Input of Input Mux Bi Ci Input Mux: Select Input of Input Mux Ci Di Input Mux: Select Input of Input Mux Di Enable Any of the 4 Input Muxes: Di/Ci/Bi/Ai Ti Input Test Mux: Select Which Input Group is Connected to Input Test Mux Enable Test Muxes: Input & Output Enable Sync Detectors for Di/Ci/Bi/Ai Ax Crosspoint Mux: Enable/Gain = 2or1/Select Input (2Bits) Bx Crosspoint Mux: Enable/Gain = 2or1/ Select Input (2Bits) Cx Crosspoint Mux: Enable/Gain = 2or1/ Select Input (2Bits) Dx Crosspoint Mux: Enable/Gain = 2or1/ Select Input (2Bits) Sx Crosspoint Mux: Enable/Gain = 2or1/ Select Input (2Bits) Sync, Overlay, and Calibration Modes Gain for: Di/Ci/Bi/Ai Set to HI for gain of 2 Set to LO for gain of 1 No Operation A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D3 S3 S3 S3 S3 EnDi TiS3 EnTi D2 S2 S2 S2 S2 EnCi TiS2 ToS2 DATA D1 S1 S1 S1 S1 EnBi TiS1 ToS1 D0 S0 S0 S0 S0 EnAi TiS0 ToS0
EnDSync EnCSync EnBSync EnASync En En En En En X AvDi=2 AV=2/ not1 AV=2/ not1 AV=2/ not1 AV=2/ not1 AV=2/ not1 Trans AvCi=2 S1 S1 S1 S1 S1 Toggle AvBi=2 S0 S0 S0 S0 S0 Autocal AvDi=2
F
1
1
1
1
X
X
X
X
Order bits are loaded
1
2
3
4
5
6
7
8
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FN7362.1 August 1, 2005
EL4544 Pin Descriptions
356-PIN BGA PIN NAME FUNCTION All input pins for 16 x R, G, B differential inputs CIRCUIT
VP
1.75k + - VM VREF 1.5V VM
CIRCUIT 1 Analog outputs
VP
VM
CIRCUIT 2 RAZ, BAZ, GAZ outputs
VP
200
VM
CIRCUIT 3 Digital inputs
VDP
VM
VM
CIRCUIT 4 Digital outputs
VDP
VM
CIRCUIT 5
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FN7362.1 August 1, 2005
EL4544 Pin Descriptions
356-PIN BGA (Continued) FUNCTION Extra inputs TMon1, TMon2 VpA, VpB, VpC, VpD, VpS VmA, VmB, VmC, VmD, VmS RefS: Reference input for output channels RefOL: Reference for overlay Inputs CIRCUIT
VP
PIN NAME
VM
CIRCUIT 6 RefA, RefB, RefC, RefD: Reference inputs for output channels A, B, C, D and for overlay inputs ROL, GOL, BOL
VP
35k VM VM
CIRCUIT 7
Functional Overview
Overall Functionality
The EL4544 is a video crosspoint switch that has 16 (RGB differential) input channels (with H & V sync embedded in their common-modes) which connect via an internal crosspoint mux to 5 (RGB + HV) single-ended output channels. The 5th output group has enhanced features that include: a pixel-by-pixel overlay mux and auto-calibrated offset cancellation. All analog and digital outputs have a high-impedance state, allowing several EL4544 to share the same output connections.
signal groups labelled A, B, C, D, and S which buffer signals from the corresponding crosspoint outputs Ax, Bx, Cx, Dx, and Sx. Each of these output groups has an independent reference pin (RefA, RefB, RefC, RefD, and RefS) that allows the user to program the reference level that corresponds to a zero voltage differential input.
Analog and Digital Video Outputs
All analog outputs (A, B, C, D, and S) have a signal range from 0V to 3.5V and are capable of driving the 150 load presented by a terminated video cable. The H & V sync outputs and all other digital I/O are compatible with 3V operation; their signal swings are determined by connecting the digital supply pin Vdp to a 3V source.
16 RGB Differential Video Inputs with Encoded Sync
For each of the 16 RGB groups of differential video inputs, horizontal and vertical sync are encoded as a combination of the common modes for each RGB group. Each of these differential input pins has a single-ended signal range that spans the entire 0V to 5V supply range. The embedded sync signals are provided by the EL4543 Triple Differential Twisted Pair Driver IC.
How to Configure the Analog Video Outputs to Swing to 0V
The RGB analog outputs of the A, B, C, D, and S output groups are all capable of a range of swing that reaches the negative supply pin Vm = 0V. However, since the EL4544 has no internal supply connections, its single-ended outputs run out of bandwidth, slew rate, and linearity below 0.5V. If accurate wide band performance below 0.5V is required, add external pulldown resistors between each analog output and an external -5V supply. This will keep the output stage biased. Values between 3k to 1k are suggested. The lower the selected resistance, the wider the bandwidth will be at 0V, but lower external resistance will increase overall IC power dissipation significantly since these resistors are loading their respective output stages.
Overall Analog Signal Flow
There are four independent internal input multiplexors represented as Ai, Bi, Ci, and Di in the block diagram and serial bus interface control table (hexa-decimal addresses 0h, 1h, 2h, 3h). These muxes convert the selected RGB differential input signal to single-ended RGB and extract H & V sync. The five output crosspoint multiplexors represented as Ax, Bx, Cx, Dx, and Sx, can independently select from the four internal (RGBHV) signal groups Ai, Bi, Ci, and Di by programming the hexadecimal serial bus addresses 8h, 9h, Ah, Bh, and Ch. There are five RGBHV single-ended output
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FN7362.1 August 1, 2005
EL4544
Operating the S Output Group Near Ground
The S output group has one additional consideration to cover configurations where the output signals and the output reference pin RefS are operated below 0.5V. Under these circumstances, each of the three auto-zero monitoring pins RAZ, GAZ, and BAZ, require an external 10k resistor connecting each to an external -5V supply. This keeps the auto-zero circuitry active all the way down to ground. voltage of pin RefS. When pin Cal is brought back to a logical "HI", the calibration is held until the next calibration cycle, and the S group will accurately convey the video signal with low offsets. A small hold-step (1mV) can be observed whenever the calibration signal is released. Each subsequent activation of the sampling phase refreshes the calibration. If Toggle mode is inactive, the user must individually calibrate both the overlay and non-overlay ("thru") output states by selecting the between them and running calibration separately for both of the input conditions. Changing the input selections by reprogramming the crosspoint to another input path or by changing the overlay mode (transparent/opaque), requires refreshing of this calibration. Ideally, the calibration is refreshed once per line of video. The drift during a line of video is negligible. (On the lab bench, using manual control, a drift rate on the order of 0.2mV/sec will be observed.)
Switchable Video Output Group Has Overlay Capability and Offset Cancellation
The S group of output signals have an overlay switch that allows single-ended inputs ROL, GOL, and BOL, to be inserted on a pixel-by-pixel basis. The pin RefOL allows the user to program the overlay input (reference) level that produces an output voltage equal to the output reference pin RefS. The S group of video outputs has an Auto-Calibration mode which can null out offsets through the entire selected signal path from its inputs to its outputs. (It is usually triggered during the front or back porch of video when the input signal is known to be at Black Level.)
Toggle Mode Automatically Supervises the Calibration Cycles
The purpose of Toggle mode is to automatically alternate between calibrating the overlay and calibrating the "thru" paths to the S Output group. The Toggle mode assumes that overlays never exist outside of the video screen (that overlay only occurs during active video). When using the Toggle mode, the overlay function must be inactive during and around sync. When Toggle mode is active and the overlay switch is disabled, the EL4544 will automatically toggle between "thru" and overlay selections for alternate pulsing of the calibrate signal. Thus, every alternate calibrate pulse will override the selected "thru" state of the overlay switch, perform an auto-zero function, and then return the overlay switch back to its original "thru" position. This is true if the programming Bit D1 in Register D (labelled Toggle) of the Serial Interface is programmed to a logical "1". Whenever the IC is reset by momentarily pulling the Reset pin "LO", the Toggle mode is initialized such that the first path calibrated is the overlay path. The next calibration cycle will automatically calibrate the "thru" path.
Transparent vs Opaque Overlays
The overlay input for the S group is directly selected by the Overlay control pin Ovl. Two types of overlay are possible. The simplest overlay alternates between the dedicated overlay input and the "thru" input (that has been selected by the cross-point multiplexor). The "transparent" overlay mode is different from the standard overlay mode in that it presents the average of the overlay input and the "thru" input signal during overlay. The transparent mode is selected either by driving the Trans pin low or by programming bit D2 in Register D of the Serial Interface to a logical "1".
Serial Interface Control of the Auto-Calibration Feature
Programming bit D0 in Register D of the Serial Interface to a logical "1" activates the "Auto-Calibration" Mode which allows offsets from all inputs to the S group to be nulled-out via a calibration sequence. The programming Bit D1 in Register D of the Serial Interface is called Toggle. It allows for two modes of auto-calibration. If Toggle is programmed to a logical "0", Toggle mode is inactive. The auto-calibration cycle must be executed separately for both input groups (the overlay and the through signal groups).
Incorrect Use of the Toggle Mode
If the overlay is selected during auto-calibration with the Toggle mode active, the "thru" path will never be calibrated. Only the overlay gets calibrated in this configuration.
Integrated Die Temperature Probes
Thermal monitoring pins TMon1 and TMon2 allow the user to effectively monitor the die temperature by lightly forward biasing internal diodes and measuring their forward voltage drop. Since these diodes will have a -2mV/C tempco, they can be an effective means of evaluating the thermal management of the user's application board and may even be configured to provide a thermally-triggered shutdown. To implement this feature, pull either of these pins below the negative supply with precision current source of 10A to 100A. Measure the forward drop at room temperature with
What Happens During an Auto-Calibration Cycle
The auto-calibration (auto-zero) feature only applies to the S group of outputs. An auto-calibration cycle works as follows for either the overlay input or a selected "thru" input from the cross-point: During any time when the input signal is known to be at a "zero-level" ("zero-level" is a differential-zero input signal for any of the 16-RGB differential inputs or when the pin voltages to the overlay inputs ROL = GOL = BOL are all equal to RefOL), setting the calibration pin Cal to a logical "LO" activates the sample phase of auto-calibration and forces the analog outputs to be equal to the reference 12
FN7362.1 August 1, 2005
EL4544
the chip disabled. During operation, every 1C rise in temperature will produce a 2mV drop in the forward voltage. inputs. The EL4543 provides this encoding as shown in Table 1.
TABLE 1. SYNC SIGNAL ENCODING COMMON MODE A (RED) 3.0 2.5 2.0 2.5 COMMON MODE B (GREEN) 2.0 3.0 3.0 2.0 COMMON MODE C (BLUE) 2.5 2.0 2.5 3.0
Some Tips on the Most Effective Programming of the EL4544
The video inputs present a 1.75k single ended and a 3.5k differential load to an incoming video signal. Since this load is in parallel with the external termination network, it has a consistent effect on the system gain. To maintain this consistency, it is inadvisable to program more than one input stage (Ai, Bi, Ci, or Di) to "look" at any given video input (RGB0, RGB1, ..., RGBF) since each activated input stage puts an additional parallel load of 3.5k onto the selected input. When programming the serial interface this is simply expressed as: Avoid programming the same value into the four data registers (for Ai, Bi, Ci, & Di) at hex addresses 0H, 1H, 2H, & 3H. They should all have unique values. This is important since if any inputs are selected more than once, their gains will mismatch an input that has only been selected once. If one wishes to broadcast the same signal to multiple output channels, this can easily be accomplished without violating the advice of the previous paragraph. Select the input that needs to be broadcast using any one of the four input selectors (Ai, Bi, Ci, or Di), then have any of up to five of the output stages (Ax, Bx, Cx, Dx, Sx) point to the input stage that is pointing to the desired input signal. These are selected using hex 8H, 9H, AH, BH, & CH. Now the EL4544 is broadcasting a single video source to multiple outputs without excessively loading down the selected input.
H Low Low High High
V High Low Low High
The EL4544 decodes the common-mode signals into H & V syncs as follows: Horizontal Sync is TRUE when the Blue_Common_Mode voltage is greater than the Average_of_Red_and_Green_Common_Mode voltage. Vertical Sync is TRUE when the Average_of_Red_and_Blue_Common_Mode voltage is greater than the Green_Common_Mode voltage. The sync comparators have an internal symmetrical hysteresis that is less than 50mV. Timing skews between comparators under all conditions are less than one pixel. The comparators have an input common mode that allows for operation at least 1V from the negative supplies and at least 1.5V from the positive supplies.
Logic Levels for Serial Interface and Control Logic
TABLE 2. INPUT LOGIC THRESHOLD (+5V SUPPLY) VLO, max VHI, min 0.8V 2V
Sync Decoding of EL4544
The EL4544 is designed to receive and decode Horizontal and Vertical Sync signals that have been encoded as common-mode signals of the Red, Green, and Blue Video
Pin Descriptions
PIN NAME Rp0 Rn0 Rp1 Rn1 Rp2 Rn2 Rp3 Rn3 Rp4 Rn4 Rp5 Rn5 Rp6 SOLDER BALL A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 Red plus input 0 Red minus input 0 Red plus input 1 Red minus input 1 Red plus input 2 Red minus input 2 Red plus input 3 Red minus input 3 Red plus input 4 Red minus input 4 Red plus input 5 Red minus input 5 Red plus input 6 DESCRIPTION EQUIVALENT CIRCUIT Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1
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FN7362.1 August 1, 2005
EL4544 Pin Descriptions (Continued)
PIN NAME Rn6 Rp7 Rn7 Vm Vp Rp8 Rn8 Rp9 Rn9 RpA RnA RpB RnB RpC RnC RpD RnD RpE RnE RpF RnF TMon1 Vp Vm BnF BpF BnE BpE BnD BpD BnC BpC BnB BpB BnA BpA Bn9 Bp9 Bn8 Bp8 SOLDER BALL B9 A10 B10 MultipleBalls C11 A11 B11 A12 B12 A13 B13 A14 B14 A15 B15 A16 B16 A17 B17 A18 B18 C18 A20 MultipleBalls C19 C20 D19 D20 E19 E20 F19 F20 G19 G20 H19 H20 J19 J20 K19 K20 Red minus input 6 Red plus input 7 Red minus input 7 Analog minus supply Analog plus supply Red plus input 8 Red minus input 8 Red plus input 9 Red minus input 9 Red plus input 10 Red minus input 10 Red plus input 11 Red minus input 11 Red plus input 12 Red minus input 12 Red plus input 13 Red minus input 13 Red plus input 14 Red minus input 14 Red plus input 15 Red minus input 15 Thermal Monitor 1 has diodes to measure die temperature Analog plus supply Analog minus supply Blue minus input 15 Blue plus input 15 Blue minus input 14 Blue plus input 14 Blue minus input 13 Blue plus input 13 Blue minus input 12 Blue plus input 12 Blue minus input 11 Blue plus input 11 Blue minus input 10 Blue plus input 10 Blue minus input 9 Blue plus input 9 Blue minus input 8 Blue plus input 8 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 6 DESCRIPTION EQUIVALENT CIRCUIT Reference Circuit 1 Reference Circuit 1
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FN7362.1 August 1, 2005
EL4544 Pin Descriptions (Continued)
PIN NAME Vp Vm Bn7 Bp7 Bn6 Bp6 Bn5 Bp5 Bn4 Bp4 Bn3 Bp3 Bn2 Bp2 Bn1 Bp1 Bn0 Bp0 Vm Vp TMon2 GnF GpF GnE GpE GnD GpD GnC GpC GnB GpB GnA GpA Gn9 Gp9 Gn8 Gp8 Vp Vm Gn7 SOLDER BALL K18 MultipleBalls L19 L20 M19 M20 N19 N20 P19 P20 R19 R20 T19 T20 U19 U20 V19 V20 Vm Y20 V18 W18 Y18 W17 Y17 W16 Y16 W15 Y15 W14 Y14 W13 Y13 W12 Y12 W11 Y11 V11 MultipleBalls W10 Analog plus supply Analog minus supply Blue minus input 7 Blue plus input 7 Blue minus input 6 Blue plus input 6 Blue minus input 5 Blue plus input 5 Blue minus input 4 Blue plus input 4 Blue minus input 3 Blue plus input 3 Blue minus input 2 Blue plus input 2 Blue minus input 1 Blue plus input 1 Blue minus input 0 Blue plus input 0 Analog minus supply Analog plus supply Thermal Monitor 2 has diodes to measure die temperature Green minus input 15 Green plus input 15 Green minus input 14 Green plus input 14 Green minus input 13 Green plus input 13 Green minus input 12 Green plus input 12 Green minus input 11 Green plus input 11 Green minus input 10 Green plus input 10 Green minus input 9 Green plus input 9 Green minus input 8 Green plus input 8 Analog plus supply Analog minus supply Green minus input 7 Reference Circuit 1 Reference Circuit 6 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 DESCRIPTION EQUIVALENT CIRCUIT
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FN7362.1 August 1, 2005
EL4544 Pin Descriptions (Continued)
PIN NAME Gp7 Gn6 Gp6 Gn5 Gp5 Gn4 Gp4 Gn3 Gp3 Gn2 Gp2 Gn1 Gp1 Gn0 Gp0 Vm Vp Chip SOLDER BALL Y10 W9 Y9 W8 Y8 W7 Y7 W6 Y6 W5 Y5 W4 Y4 W3 Y3 Vm V3 V5 Green plus input 7 Green minus input 6 Green plus input 6 Green minus input 5 Green plus input 5 Green minus input 4 Green plus input 4 Green minus input 3 Green plus input 3 Green minus input 2 Green plus input 2 Green minus input 1 Green plus input 1 Green minus input 0 Green plus input 0 Analog minus supply Analog plus supply Chip enable (active low): when "HI" disables all analog except references; all analog or digital video outputs are in a high impedance state; all registers hold their data but remain programmable since the serial interface is left active Digital logic power supply: nominally at 3V Reset (active low): clears all registers in interface and calibration sections; this causes the chip to standby with all outputs in a high impedance state Serial bus enable (active low): enables the serial bus when "LO"; latches the current value when transitioning to "HI" Analog plus supply Analog minus supply Serial bus clock Serial bus data output Serial bus data input Output stage reference level (input) A RGB video output stages' minus supply A Blue output A Vertical sync output A Green output A Horizontal sync output A Red output A RGB video output stages' plus supply A Output stage reference level (input) B RGB video output stages' minus supply B Reference Circuit 4 Reference Circuit 4 Reference Circuit 5 Reference Circuit 6 Reference Circuit 7 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 7 Reference Circuit 6 Reference Circuit 7 Reference Circuit 4 Reference Circuit 4 DESCRIPTION EQUIVALENT CIRCUIT Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1 Reference Circuit 1
Vdp Reset
U5 V4
sEn Vp Vm sClk sDo sDi RefA VmA Ba Va Ga Ha Ra VpA RefB VmB
U4 V3 MultipleBalls U3 T4 T3 Y1 Y2 W1 W2 V1 V2 U1 U2 T1 T2
Reference Circuit 4
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FN7362.1 August 1, 2005
EL4544 Pin Descriptions (Continued)
PIN NAME Bb Vb Gb Hb Rb VpB RefC VmC Bc Vc Gc Hc Rc VpC RefD VmD Bd Vd Gd Hd Rd VpD RefS VmS Bs Vs Gs Hs Rs VpS BOL GOL ROL RefOL Vm BAZ GAZ Vp RAZ Vdp SOLDER BALL R1 R2 P1 P2 N1 N2 M1 M2 L1 L2 K1 K2 J1 J2 H1 H2 G1 G2 F1 F2 E1 E2 D1 D2 C1 C2 B1 B2 A1 A2 E3 E4 D4 D5 MultipleBalls F4 D6 C3 C6 U5 Blue output B Vertical sync output B Green output B Horizontal sync output B Red output B RGB video output stages' plus supply B Output stage reference level (input) C RGB video output stages' minus supply C Blue output C Vertical sync output C Green output C Horizontal sync output C Red output C RGB video output stages' plus supply C Output stage reference level (input) D RGB video output stages' minus supply D Blue output D Vertical sync output D Green output D Horizontal sync output D Red output D RGB video output stages' plus supply D Output stage reference level (input) S RGB video output stages' minus supply S Blue output S Vertical sync output S Green output S Horizontal sync output S Red output S RGB video output stages' plus supply S Blue overlay input for output group S Green overlay input for output group S Red overlay input for output group S Overlay inputs' reference level for output group S Analog minus supply Blue auto-zero internal calibration level monitor for output group S Reference Circuit 3 DESCRIPTION EQUIVALENT CIRCUIT Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 7 Reference Circuit 6 Reference Circuit 7 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 7 Reference Circuit 6 Reference Circuit 7 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 7 Reference Circuit 6 Reference Circuit 7 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 5 Reference Circuit 2 Reference Circuit 7 Reference Circuit 6 Reference Circuit 6 Reference Circuit 6 Reference Circuit 6
Green auto-zero internal calibration level monitor for output group S Reference Circuit 3 Analog plus supply Red auto zero internal calibration level monitor for output group S Digital logic power supply: nominally at 3V Reference Circuit 3
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FN7362.1 August 1, 2005
EL4544 Pin Descriptions (Continued)
PIN NAME Ovl Cal Trans Vp Vm Vm Vm SOLDER BALL D3 C4 C5 C3 MultipleBalls A19 B19, B20, C7, C8, C9, C10, C12, C13, C14, C15, C16, C17, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, E17, E18, F3, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F17, F18, G3, G4, G6, G7, G8, G9, G10, G11, G12, G13, G14, G15, G17, G18, H3, H4, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H17, H18, J3, J4, J6, J7, J8, J9, J10, J11, J12, J13, J14, J15, J17, J18, K3, K4, K6, K7, K8, K9, K10, K11, K12, K13, K14, K15, K17, L3, L4, L6, L7, L8, L9, L10, L11, L12, L13, L14, L15, L17, L18, M3, M4, M6, M7, M8, M9, M10, M11, M12, M13, M14, M15, M17, M18, N3, N4, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N17, N18, P3, P4, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P17, P18, R3, R4, R6, R7, R8, R9, R10, R11, R12, R13, R1, R15, R17, R18, T17, T18, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, U17, U18, V7, V8, V9, V10, V12, V13, V14, V15, V16, V17, W19, W20, Y19 U6, V6 Not connected; may be grounded DESCRIPTION Digital input to select whether overlay is active for output group S Digital input to calibrate S output group Digital input to select a transparent overlay for output group S Analog plus supply Analog minus supply Analog minus supply EQUIVALENT CIRCUIT Reference Circuit 4 Reference Circuit 4 Reference Circuit 4
N/C
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FN7362.1 August 1, 2005
EL4544 Typical Performance Curves
5 5 DIFFERENTIAL INPUTS 3 AVIN=1 AVOUT=1 1 DIFFERENTIAL INPUTS AVIN=1 3 AVOUT=1 OUTPUT CHANNELS=R, B, G 1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
BLUE RED
-1 INPUTS 0-15 OUT Ax TYPICAL
-1
GREEN
-3
-3
-5 100K
1M
10M FREQUENCY (Hz)
100M
1G
-5 100K
1M
10M FREQUENCY (Hz)
100M
500M
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS INPUT CHANNELS
5 AVIN=1 AVOUT=1
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS OUTPUT COLOR CHANNELS
5 AVIN=1 AVOUT=1
NORMALIZED GAIN (dB)
1
NORMALIZED GAIN (dB)
3
3
1
-1 INPUTS 0-15 OUT Ax TYPICAL
-1 INPUTS 0-15 OUT Ax TYPICAL
-3
-3
-5 100K
1M
10M FREQUENCY (Hz)
100M
1G
-5 100K
1M
10M FREQUENCY (Hz)
100M
500M
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS NON INVERTING INPUTS
5
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS INVERTING INPUTS
5
NON-INVERTING INPUTS NORMALIZED GAIN (dB) 3
INVERTING INPUTS
NORMALIZED GAIN (dB)
3
1 AVIN=1, AVOUT=2 AVIN=2, AVOUT=2 -3 AVIN=1, AVOUT=1 AVIN=2, AVOUT=1 -5 100K 1M 10M FREQUENCY (Hz) 100M 1G
1 AVIN=1, AVOUT=2 AVIN=2, AVOUT=2 -3 AVIN=1, AVOUT=1 AVIN=2, AVOUT=1 1M 10M FREQUENCY (Hz) 100M 1G
-1
-1
-5 100K
FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS GAINS
FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS GAINS
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FN7362.1 August 1, 2005
EL4544 Typical Performance Curves
5 NORMALIZED GAIN (dB)
(Continued)
5
NORMALIZED GAIN (dB)
3 AVIN=2, AVOUT=1 1 AVIN=1, AVOUT=1 AVIN=1, AVOUT=2 (-0.1dB 180MHz) AVIN=2, AVOUT=2 (-0.1dB 150MHz) 1M 10M FREQUENCY (Hz) 100M 1G
ALL OUTPUT MUXes ENABLED OR DISABLED 3 NO EFFECT
1
-1
-1
-3
-3
-5 100K
-5 100K
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS GAIN COMBINATIONS
5
FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS INPUT MUX LOADING
5
AVIN=1 AVOUT=1 NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3 GPO GNO
Sx OUTPUT CHANNEL IN OVERLAY MODE
3
1
1 GAIN=1 -1
-1
-3
-3
GAIN=2 1M 10M FREQUENCY (Hz) 100M 1G
-5 100K
1M
10M FREQUENCY (Hz)
100M
1G
-5 100K
FIGURE 9. GAIN vs FREQUENCY DIFFERENTIAL INPUT COMPARISON
5 INPUT=OVERLAY OUTPUT=Sx 3 AVIN=2 AUTO CAL DISABLED -3dB 390MHz
FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS GAINS
5
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
Sx OUTPUT CHANNEL IN OVERLAY MODE 3 AVIN=1 AUTO CAL DISABLED -3dB 322MHz
1
1
-1 AUTO CAL ENABLED -3dB 192MHz
-1 AUTO CAL ENABLED -3dB 192MHz
-3
-3
-5 100K
1M
10M FREQUENCY (Hz)
100M
1G
-5 100K
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 11. GAIN vs FREQUENCY FOR Sx CHANNEL FUNCTIONS
FIGURE 12. GAIN vs FREQUENCY FOR Sx CHANNEL FUNCTIONS
20
FN7362.1 August 1, 2005
EL4544 Typical Performance Curves
5 INPUT=OVERLAY OUTPUT=Sx 3 AUTO CAL=DISABLED AVIN=2 3dB=390MHz
(Continued)
5
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
INPUT=OVERLAY OUTPUT=Sx 3 AUTO CAL=ENABLED AVIN=2 3dB 176MHz
1
1
-1 AVIN=AVOUT=1 3dB 322MHz
-1 AVIN=AVOUT=1 3dB 162MHz
-3
-3
-5 100K
1M
10M FREQUENCY (Hz)
100M
1G
-5 100K
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS GAINS
7 VA=VARIOUS VD=3.0V REFOUT=1.5V AVIN=2 4.43V 4.45V 4.47V 4.5V 4.55V 4.6V 4.7V 5V
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS GAINS
-30 INPUT TO OUTPUT DISABLED (dB)
AVTOTAL=4
NORMALIZED GAIN (dB)
5
-50
3
-70
1
-90
-1 4.42V -3 100K 1M 10M FREQUENCY (Hz) 100M 500M
-110
-130 100K
1M
10M FREQUENCY (Hz)
100M
500M
FIGURE 15. PEAKING FOR VARIOUS POWER SUPPLY SETTINGS
-30
FIGURE 16. INPUT TO OUTPUT ISOLATION (DISABLED)
INPUT SIGNAL -20dBm
-30 AVTOTAL=4 CROSSTALK (dB) AVIN=2 -50
AVIN=2
-50 CROSSTALK (dB)
Ax IN Bx LISTEN BROADCAST Ax IN Bx LISTEN Ax ON Bx ON Ax IN Bx LISTEN Ax Cx Dx ON Ax IN Bx LISTEN ALL OTHERS OFF 1M 10M FREQUENCY (Hz) 100M 500M
-70 AVIN=1 -90
-70
-90
-110
-110
-130 100K
1M
10M FREQUENCY (Hz)
100M
500M
-130 100K
FIGURE 17. CROSSTALK FOR VARIOUS GAINS
FIGURE 18. CROSSTALK FOR VARIOUS BROADCAST MODES
21
FN7362.1 August 1, 2005
EL4544 Typical Performance Curves
25
(Continued)
25
GROUP DELAY (5ns/DIV)
5
GROUP DELAY (5ns/DIV)
15
15
5
-5
-5
-15
-15
-25 100K
1M
10M FREQUENCY (Hz)
100M
500M
-25 100K
1M
10M FREQUENCY (Hz)
100M
500M
FIGURE 19. GROUP DELAY FOR OUTPUT CHANNELS A, B, C, D, S
10 AVIN=2 -10 CMRR (dB) OUTPUT IMPEDANCE ()
FIGURE 20. GROUP DELAY FOR OVERLAY MODE
300
AVIN=2
200
-30
150
-50
100
-70
50
-90 100K
1M
10M FREQUENCY (Hz)
100M
500M
0 10K
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 21. CMRR
700 600 1K SLEW RATE (V/s) 500
FIGURE 22. OUTPUT IMPEDANCE
10K VOLTAGE NOISE (nV/Hz)
AVIN=2 400 300 200 100
100
10 100
1K
10K
100K
1M
10M
100M
0
3
3.5
4
4.5
5
5.5
6
6.5
7
FREQUENCY (Hz)
SUPPLY VOLTAGE (VD) VOLTS
FIGURE 23. VOLTAGE NOISE vs FREQUENCY
FIGURE 24. SLEW RATE vs SUPPLY (VD)
22
FN7362.1 August 1, 2005
EL4544 Typical Performance Curves
(Continued)
VOLTAGE (500mV/DIV)
OUTPUT
VOLTAGE (500mV/DIV)
AVIN=1 AVOUT=1 GPO
OUTPUT
INPUT
INPUT AVIN=1 AVOUT=1 GNO TIME (10ns/DIV)
TIME (10ns/DIV)
FIGURE 25. SMALL SIGNAL NEGATIVE PULSE RESPONSE
FIGURE 26. SMALL SIGNAL POSITIVE PULSE RESPONSE
OUTPUT VOLTAGE (500mV/DIV) OUTPUT VOLTAGE (500mV/DIV)
INPUT AVIN=1 AVOUT=1 GPO TIME (10ns/DIV)
INPUT
AVIN=1 AVOUT=1 GNO TIME (10ns/DIV)
FIGURE 27. LARGE SIGNAL NEGATIVE PULSE RESPONSE
FIGURE 28. LARGE SIGNAL POSITIVE PULSE RESPONSE
VOLTAGE (500mV/DIV)
VOLTAGE (500mV/DIV)
20ns ENABLE PULSE (STEP)
940ns
ENABLE PULSE (STEP)
GATED OUTPUT SIGNAL
GATED OUTPUT SIGNAL
TIME (1.0s/DIV)
TIME (1ns/DIV)
FIGURE 29. ENABLE TIME
FIGURE 30. DISABLE TIME
23
FN7362.1 August 1, 2005
EL4544 Typical Performance Curves
400 350 SUPPLY CURRENT (mA) 300 250 200 150 100 50 0 0 1 Va=5.0V Vd=3.0V RefOL=1.5V 0 2 3 4 5 NUMBER OF OUTPUT MUXES ENABLED 0 1 2 SUPPLY CURRENT (mA)
(Continued)
600 500 400 300 200 100 Va=5.0V Vd=3.0V RefOL=1.5V 3 4 5 6 7 8 9 INPUT MUXES 1 - 4 ENABLED OUTPUT MUXES 1 - 5 ENABLED
NUMBER OF MUXES ENABLED 1 -5 (OUTPUT MUXES) 5 - 9 (INPUT MUXES)
FIGURE 31. POWER SUPPLY CURRENT AS FUNCTION OF OUTPUT MUXES ENABLED - ALL INPUT MUXES DISABLED
FIGURE 32. POWER SUPPLY CURRENT AS FUNCTION OF INPUT & OUTPUT MUXES ENABLED
600 Va SUPPLY CURRENT (mA) 550 500 450 400 350 Va=5.0V Vd=3.0V RefOL=1.5V 300 1 1.5 2 2.5 3 3.5 4
300 250 200 150 100 50 Va=5.0V Vd=3.0V RefOL=1.5V 0 0 1 2 3 4
SUPPLY CURRENT (mA)
NUMBER OF INPUT MUXES ENABLED
NUMBER OF INPUT MUXES ENABLED
FIGURE 33. POWER SUPPLY CURRENT AS FUNCTION OF INPUT MUXES ENABLED - ALL OUTPUT MUXES ENABLED
FIGURE 34. POWER SUPPLY CURRENT AS FUNCTION OF INPUT MUXES ENABLED - ALL OUTPUT MUXES DISABLED
500 ANALOG SUPPLY/QUIESCENT/ CURRENT (mA) 450 SUPPLY CURRENT (mA) 400 350 300 250 200 150 100 50 0 0 0.5 1 1.5 2 2.5 3
120 100 80 60 40 20 0 MAIN VOLTAGE SUPPLY (Va) Vd=3.0V RefOL=1.5V 2 2.5 3 3.5 4 4.5 5 5.5
DIGITAL SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 35. ANALOG CURRENT vs DIGITAL SUPPLY VOLTAGE
FIGURE 36. SUPPLY CURRENT VERSUS SUPPLY VOLTAGE BASE LINE IDLE - ALL INPUTS AND OUTPUTS DISABLED
24
FN7362.1 August 1, 2005
EL4544 Typical Performance Curves
40 35 30 IP3 (dBm) 25 20 15 10 5 0 1.0 10.0 FREQUENCY (MHz) 100.0 AVTOTAL=4 AVIN=2 IP3 (dBm) AVIN=1
(Continued)
40 35 30 25 20 15 10 5 0 1.0 10.0 FREQUENCY (MHz) 100.0 AVIN=1 AVIN=2 AVTOTAL=4
FIGURE 37. THIRD-ORDER INTERCEPT POINT vs FREQUENCY GREEN CHANNEL
FIGURE 38. THIRD-ORDER INTERCEPT POINT vs FREQUENCY BLUE CHANNEL
40 35 30 IP3 (dBm) 25 20 15 10 5 0 1.0 10.0 FREQUENCY (MHz) 100.0 AVIN=1 AVIN=2 AVTOTAL=4 AMPLITUDE (dBm)
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
AVTOTAL=4 f1=10MHz f2=10.004MHz f1
IP3= 36.2 f2
2f1-f2
2f2-f1
-110 9.995 9.997 9.999 10.001 10.003 10.005 10.007 10.009 FREQUENCY (MHz)
FIGURE 39. THIRD-ORDER INTERCEPT POINT vs FREQUENCY RED CHANNEL
FIGURE 40. IP3 AVTOTAL = 4 BLUE CHANNEL
0 AVIN=2 -10 f1=10MHz -20 f2=10.004MHz AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100 2f1-f2 f1 f2
0 IP3=33.9 -10 -20 AMPLITUDE (dBm) -30 -40 -50 -60 -70 -80 -90 -100
AVIN=1 f1=10MHz f2=10.004MHz f1 f2
IP3 = 24.5
2f2-f1
2f1-f2
2f2-f1
-110 9.995 9.997 9.999 10.001 10.003 10.005 10.007 10.009 FREQUENCY (MHz)
-110 9.995 9.997 9.999 10.001 10.003 10.005 10.007 10.009 FREQUENCY (MHz)
FIGURE 41. IP3 AVIN = 2 BLUE CHANNEL
FIGURE 42. IP3 AVIN = 1 BLUE CHANNEL
25
FN7362.1 August 1, 2005
EL4544
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 26
FN7362.1 August 1, 2005

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